With the development of semiconductor processing technologies, the dimensions of semiconductor process nodes continue to decrease according to Moore's law. To adapt to the decrease of semiconductor process nodes, the channel length of a MOSFET needs to be reduced continuously. A shorter channel length can provide advantages such as an increased density of semiconductor chips and an increased switching speed of the MOSFETs.
However, as the channel lengths of devices decrease, the distance between the source electrode and the drain electrode of a device is also reduced. As such, the control ability of the gate electrode over the channel is reduced, causing a subthreshold leakage phenomenon. In other words, short-channel effects (SCE) are more likely to occur.
To better adapt to the needs of proportionally scaling down device dimensions, the focus of semiconductor fabrication gradually changes from planar MOSFETs to three-dimensional transistors that have higher performance, such as fin-FETs. In a fin-FET, the gate electrode can provide control over an ultra-thin body (a fin structure) from both sides, and thus gate electrode has an increased control over the channel compared to planar MOSFET devices. Accordingly, short-channel effects may be well suppressed. Further, compared to other types of devices, fin-FETs are more compatible with the manufacturing technologies of current integrated circuits.
However, the electrical performance of fin-FETs formed by conventional technologies need to be improved.
The disclosed devices and methods are directed to solve one or more problems set forth above and other problems.